1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to an etch process for making integrated circuit devices.
2. Description of the Related Art
As the size and scaling of semiconductor device technology is reduced, the requirements for device design and fabrication—such as controlling the thickness of thinner gate dielectric and other constituent layers, better uniformity control and/or obtaining thinner film thicknesses—continue to tighten. In addition, leakage current due to underlying substrate damage created during fabrication is an additional problem with smaller devices. An additional challenge posed by decreasing feature sizes is that aspects of device design and fabrication that previously gave rise to only second-order effects in long-channel devices can no longer be ignored. For example, the reduced scaling of channel length and gate oxide thickness in a conventional MOS transistor exacerbates problems of polysilicon gate depletion, high gate resistance, high gate tunneling leakage current and dopant (i.e., boron) penetration into the channel region of the device. As a result, CMOS technology, which once relied on polysilicon as a gate conductor and silicon dioxide as a gate dielectric, now contemplates the use of dual-metal gate conductors and high dielectric constant (high-k) dielectrics. While high-k gate dielectric materials advantageously exhibit a relatively high dielectric constant (k) to enable the deposition of thicker gate dielectric layers without adversely affecting the physical and electrical thickness characteristics of the deposited dielectric layer (compared with thinner silicon dioxide dielectric layers), such high-k materials can be difficult to etch with conventional etchant techniques, making it difficult to control the layer thickness of such materials.
In addition to enhancements in the gate dielectric, substantial interest has been engendered in the use of metal layers with smaller semiconductor devices, such as metal gates used as an alternative to polysilicon or metal glue layers used with metal interconnects. For example, metal gates not only obviate gate-depletion and boron-penetration effects, but also provide a significantly lower sheet resistance. However, the use of high-k gate dielectric layers and metal gate devices creates new design challenges, such as pinning the work function of the gate electrodes toward the middle of the silicon band gap, which has a negative impact on device parameters including threshold voltage and drive current which can be different for NMOS and PMOS devices. This has led investigators into dual gate dielectric materials. Hence, CMOS processes may use a certain high-k material for the NMOS devices, while a different material might be used for the PMOS devices.
One typical manufacturing technique for advanced integrated circuits is the use of different dielectric thicknesses to optimize transistor performance for p-type or n-type transistors and for the various circuit elements such as logic and memory components on the same chip. With silicon dioxide as the dielectric, the different thickness can be selectivity grown and removed from various potions of the circuit; however, this is not possible with a deposited dielectric, especially for the more difficult to etch high-k metallic oxide dielectrics. In addition, as the dielectric thickness is further scaled down, the control needed is truly on the atomic level since dielectric thickness differences of 5-20 nm may be needed for the different transistors.
Accordingly, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.